The present invention generally relates to electronic devices and integrated circuit chips and, more particularly, to non-volatile, electronically programmable memory for integrated circuit electronic devices.
There are several uses and applications for an electronic fuse, sometimes referred to in the art as an “eFUSE”, including, for example, array redundancy for large cache memories in microprocessor chips, electronic chip identification, part number identification, and thermal diode calibration. In a redundancy application, for example, chips returned from fabrication are usually tested and a certain percentage of them are usually found to be bad, for example, from random contingencies that may occur in the fabrication process. The percentage of good, usable chips is commonly referred to as the “yield”. Redundancy may enable programming a chip at the testing phase so that flawed portions of the chip are not used in favor of unflawed redundant portions, thereby increasing the yield and decreasing the percentage of chips that must be thrown away as unusable. Most of the applications for electronic fuses combine the electronic fuse with the use of a memory in some way, for example, as part of a memory bitcell. For example, in electronic chip identification or part number identification, an electronic fuse may be used to “program” or write information into a non-volatile memory, which may be comprised of memory bitcells, and the information can then be read from the memory as a unique chip identifier or part number identifier. Also, for example, in thermal diode calibration, a non-volatile memory programmed using electronic fuses can be used to hold a test temperature and the thermal diode voltage read at the test temperature.
FIG. 1 shows a prior art memory bitcell 100 for writing, storing, and reading one bit of information. Memory bitcell 100 may include circuitry for a scannable flip-flop, or latch, 102, fuse-sensing circuitry 104, fuse-programming circuitry 106, and clamp circuitry 108. Memory bitcell 100 may also include a clock buffer 110, which may provide a clock signal 112 and a complement 114 of clock signal 112 from a single phase clock. FIG. 2 shows another memory bitcell 101, which may use two-phase clock signaling as opposed to the single phase clock signaling used by the memory bitcell 100 shown in FIG. 1. Memory bitcell 101 is similar to memory bitcell 100 and may include scannable flip-flop or latch 103, fuse-sensing circuitry 104, fuse-programming circuitry 106, and clamp circuitry 108. Circuitry for latch 103 may be similar to circuitry for latch 102 except that latch 103 may be driven by two-phase clocks providing clock signal 116 (labeled φ1 in FIG. 2) and its complement 117 (φ1b) and clock signal 118 (φ2) and its complement 119 (φ2b).
Referring now to both FIGS. 1 and 2, when sense transistor 121 (“M7”) is turned off, for example, by providing an appropriate voltage at its gate 123 (“SENSE_FUSE”)—also referred to as SENSE_FUSE being set to “off”—latches 102, 103 may be operated independently of the rest of the circuitry—such as fuse-sensing circuitry 104, fuse-programming circuitry 106, and clamp circuitry 108—latches 102, 103 being effectively isolated when transistor 121 is off. For example, with transistor 121 turned off, either of latches 102, 103 may be operated as a scannable flip-flop. For example, a given number, say 64, of latches 102 may be chained together, the output 120 (“SOUT”) of a given latch 102 being connected to the input 122 (“SIN”) of the next latch 102 in line. Then the chain of latches 102, in this case 64 latches 102, will store a sequence of bits fed into the input 122 of the first latch 102, referred to as “scanning in” the sequence; the chain of latches 102 may be referred to as a “scan chain”. In this example, only the most recently entered 64 bits of any sequence entered will be stored because there are only 64 latches 102 chained together.
Fuse-programming circuitry 106 of memory bitcells 100, 101 may include a fuse 124. Fuse 124 may be fabricated, for example, using polysilicon with a metalized layer of silicide on top, as known in the art. Memory bitcells 100, 101 may be programmed, e.g., a sequence that has been scanned in may be permanently, or nonvolatilely, stored, by either blowing or not blowing fuse 124. Fuse 124 may be blown, for example, by providing sufficient voltage across the fuse and current flow through the fuse to destroy the fuse or alter its electrical properties, e.g., the resistance, of the fuse. For example, an unblown fuse may have a nominal resistance of about 100 ohms between terminals 126 and 128 of fuse 124, and a blown fuse may have a nominal resistance of about 5,000 ohms between terminals 126 and 128. Then, for example, a memory bitcell 100 or 101 with a blown fuse may be used to nonvolatilely store a “0” bit, and a memory bitcell 100 or 101 with an unblown fuse may be used to nonvolatilely store a “1” bit (or vice versa depending on the logic representation being used).
Fuse 124 may be programmed by providing an appropriate “on” or “off” signal at gate 130 of programming transistor 132 (“M9”). The signal at gate 130 may be provided, for example, as an AND operation of two inputs 134 and 136 by AND logic provided by NAND gate 138 and inverter 140. Input 134, for example, may be provided to all fuses simultaneously, e.g., all fuses for a chain of latches 102 as described above, so that because of the AND logic any particular fuse may be blown only when both input 134 is high and the distinct input 136 for that particular fuse is also high. Thus, programming only occurs when input 134 is high and accidental blowing of fuses from high inputs 136 may be prevented when input 134 is low. Assuming that it is desired to blow fuse 124, both inputs 134 and 136 may be set high, producing a high or “on” signal at gate 130 of programming transistor 132, allowing transistor 132 to conduct so that voltage 142 (“VDD—4_BLOW”) may be applied at terminal 126 of fuse 124 and cause current to flow through fuse 124 and transistor 132 to node 144, which may be a ground, for example. Sense transistor 121 and clamp transistor 148 should be off during fuse programming operations.
In order to blow the fuse, 10 milliamps (mA) of current is typically required to flow through the fuse 124 and transistor 132. Conventional memory bitcells—such as bitcells 100, 101—typically drive the gate 130 of transistor 132 with a voltage of 1.2 volts (V). Therefore, to make 10 mA of current flow through programming transistor 132, the drain voltage of transistor 132 must be raised very high, usually accomplished by making VDD—4_BLOW voltage 142 nominally about 3.5 V and at least in excess of 3.0 V. Thus, programming transistor 132 operates in its inefficient saturation region during the fuse programming operation.
The relatively high voltage required for blowing the fuse (e.g. VDD—4_BLOW voltage 142) produces several disadvantages. For example, any transistor in electrical proximity to the fuse 124—such as programming transistor 132—must be fabricated as a thick oxide transistor so that damage due to the high voltages and currents associated with fuse 124 can be avoided. (Thick oxide transistors are indicated in the figures by a thick dark band used to represent the channel, and thin oxide transistors are indicated in the figures by a normal thickness line used to represent the channel.) Thus, sense transistor 121 typically requires a protection transistor 146 (“M8”) of thick oxide, which may be biased to always be on, and the sole function of which is to electrically isolate and protect sense transistor 121 from fuse 124. Similarly, clamp transistor 148 (“M10”) is also typically required to made of thick oxide.
In addition, the relatively high fuse blow programming voltage 142 and consequent high drain voltage on programming transistor 132 (as described above) requires that programming transistor 132 have a large area on the chip. For example, programming transistor 132 typically has a width of about 40 microns and overall bitcell area typically is about 184.85 square microns.
As can be seen, there is a need for a memory bitcell that operates at a lower voltage than prior art memory bitcells. There is also a need for a non-volatile memory that reduces the size of integrated circuit elements used to implement the non-volatile memory.